‘Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST’, IEEE Transactions on Very Large Scale

The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel, scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the Logic BIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target Fault Coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared to recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.